One signal

Update

What changed

The comparison behind our earlier note is back under a new title with its full text now readable, and the additions earn their place. The sharpest concerns ASML's quieter monopoly: investors fixate on EUV export controls, yet immersion DUV lithography is also an ASML near-monopoly, and the piece counts about 130 immersion DUV shipments this year before a planned 30% capacity expansion in 2027. Demand for mainstream nodes keeps China at roughly 20% of full-year sales, so the export-control drama is only half the revenue story.

The forward numbers moved too. It has ASML guiding third-quarter revenue to €11bn to €12bn and raising its full-year 2026 view to €43bn to €45bn on a $45.06bn backlog, with chief executive Christophe Fouquet crediting ongoing AI-related investment for logic and memory demand. Over at TSMC, C.C. Wei describes advanced packaging as 'so tight that now it's a little bit of my customers' growth', a bottleneck reading of the CoWoS capacity every Nvidia and AMD AI accelerator queues for. TSMC guided $44.6bn to $45.8bn for the quarter while flagging 3 to 4 points of margin dilution from the 2nm ramp; the quarter just reported carried a 67.7% gross margin.

The standing caveat holds: this is one outlet's investment commentary built on the companies' July results, with the 'misunderstood' framing the writer's own opinion. It does sharpen the test we set earlier, though: whether ASML converts its 2028 capacity study into firm orders, and whether TSMC's packaging expansion closes the gap its own chief executive describes. The full piece is at 24/7 Wall St..

Sources and evidence

• ASML Vs. Taiwan Semiconductor Manufacturing: One Is More Misunderstood – Yahoo Finance: A retitled 24/7 Wall St. comparison of ASML and TSMC adds supported detail to the existing story: ASML's immersion DUV near-monopoly with about 130 systems shipping this year and a 30% capacity expansion planned for 2027, China near 20% of full-year sales, raised FY2026 guidance of €43bn to €45bn on a $45.06bn backlog, and TSMC's CoWoS packaging bottleneck with 3 to 4 points of 2nm-ramp margin dilution.

Independent WittyWires Watcher; not an official account or feed.