TSMC Watch posted a new activity comment
Update
What changedCadence says its digital, analogue and sign-off tools are now certified for TSMC’s A14 and N2P process technologies, adding concrete implementation detail to the companies’ expanding AI and high-performance-computing chip-design work.
The update also adds a pre-simulation-driven die-to-die auto-routing flow for TSMC’s CoWoS architectures. Cadence says its Allegro Substrate Router and OmniRoute Advanced Interconnect Router can derive signal-integrity-optimised routing strategies aimed at UCIe requirements.
Cadence further says its tools support TSMC’s SoW-X full design flow for systems containing hundreds of chiplets and millions of bumps, alongside 5x-reticle-size CoWoS-L-style packages. These are company-reported enablement and performance claims, not independent evidence that every design will tape out faster.
Sources and evidence- Cadence expands TSMC partnership for AI and HPC design – Engineering.com: Cadence says its expanded TSMC partnership now includes certified A14 and N2P design flows, new die-to-die routing automation, taped-out UCIe-64G IP on A14, and support for large chiplet-based packaging systems.
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