openTPU uses AI agents to design an AI accelerator, then runs models on an FPGA

An open-source project called openTPU uses AI agents in the design of an AI accelerator and has run several language models on a physical FPGA card. Its reported results offer a concrete, inspectable experiment in AI-designed hardware, though memory access is currently the bottleneck.

Watch Desk analysis

What happened

GIGAZINE reports that openTPU’s developers programmed the design onto an AMD FPGA card and ran Qwen3, Qwen3.5 and Gemma 4. They also report running the 34.7-billion-parameter Qwen3.5-35B-A3B at 3.95 tokens per second, sending model data from a PC when it would not fit in the card’s memory.

The project combines a sequencer, data transfer, matrix and vector units, and quantisation. Its deliberately simple design exposes how many clock cycles each operation takes. The report describes the software and circuitry as publicly available under the Apache 2.0 licence. Read GIGAZINE’s report.

Why it matters

This is more than an AI tool sketching a chip diagram: the reported design has been programmed onto hardware and used to run models. That makes openTPU a useful case study for anyone interested in where AI-assisted hardware design can get today, and what still gets in its way.

The immediate constraint is not the AI maths, according to the report, but the speed of reading model data from memory. That distinction matters: a working accelerator is an achievement, but it is not yet evidence of a fast or competitive alternative to established hardware.

Our read

The interesting result is the whole chain, from AI-assisted hardware design to models running on an FPGA. The reported throughput is modest, and the developers’ figures are not an independent benchmark, but this is a tangible experiment rather than a grand claim about machines designing their own successors. The Apache-licensed project could be useful to developers and educators who want to inspect how an accelerator works, not just admire a performance chart.

What to watch

• Whether the developers improve memory access and prefill performance.
• Which models and workloads can be run reliably on the FPGA.
• Whether the project publishes enough implementation detail for others to reproduce its results.

Discussion spark: For an open-source AI accelerator, what matters more at this stage: that AI helped design hardware which runs real models, or that its performance can compete with established chips?

Watch Desk is operated by WittyWires as an independent cross-cutting AI news tracker. It does not speak for the organisations or people it covers.