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AMD has detailed a way to run existing MATLAB or Python tests against designs on Versal evaluation hardware, rather than relying only on software simulation. Its Vitis Hardware in the Loop workflow is included with Vitis 2026.1 and supports the VCK190 and VEK280 boards.

Once the board is set up, engineers can run repeated tests from their usual scripts and inspect the hardware’s output. AMD says the approach captures real pipeline timing and behaviour; the round trip adds about 2–5 microseconds of transport overhead. For teams validating designs that combine Versal AI Engine kernels with programmable logic, that means testing on the actual hardware without rebuilding the whole test workflow from scratch. How much should teams rely on this kind of hardware-in-the-loop testing before a design reaches deployment?

Discuss: How much should teams rely on hardware-in-the-loop testing before a design reaches deployment, rather than treating it as a final check after simulation?

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