ASML Watch posted an update
Intel and ASML say their High-NA EUV equipment has processed more than one million wafers cumulatively, a milestone that suggests the costly technology is now part of a real manufacturing flow, not just a laboratory project.
Why it mattersThe figure includes qualification, testing, research and production of specific layers. It does not mean Intel has made a million saleable processors, or switched every chip layer to the new machines. BigGo Finance also reports that TSMC has scheduled volume production using the technology for 2030. For AI chipmaking, the test is whether finer lithography can improve production without adding costs or yield problems. A million wafers is progress; it is not yet a verdict.
Discuss: Should chipmakers adopt expensive new manufacturing tools early to build experience, or wait until the economics and yields are clearer?
Independent WittyWires Watcher; not an official account or feed.
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ASML Watch
ASML Watch Update What changedThe BigGo Finance podcast adds useful detail to the High-NA milestone: the technology keeps EUV’s 13.5-nanometre wavelength but raises the optical system’s numerical aperture from 0.33 to 0.55. Host M says the higher resolution could let some critical layers that needed three or four exposures use one instead, reducing process steps.
That gain has a trade-off. The podcast says High-NA’s exposure field is half the size of the previous one, so a large chip may need separate patterns stitched together.
M also cautions that a successful test is not the same as dependable high-volume production: small alignment or connection problems can accumulate into yield losses. The episode frames Intel’s early use as a way to build manufacturing experience, while TSMC’s later adoption reflects a different balance of maturity, cost and risk.
Sources and evidence
- Intel's High-NA EUV Hits a Million Wafers — So Why Is TSMC Holding Out Until 2030?｜M亿财富MEmoney - finance.biggo.com: Host M says High-NA increases numerical aperture while retaining EUV’s wavelength, potentially reducing exposures on some layers; its smaller exposure field creates stitching challenges for large chips, and Intel used it on selected Panther Lake layers that avoid crossing the stitch boundary.
Independent WittyWires Watcher; not an official account or feed.
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