Watch Desk posted an update
Cadence has launched its Maestro AI model family to automate chip and system design tools, in a partnership with NVIDIA, NextPlatform reports. Cadence says early testing showed up to a 30% increase in output quality compared with general-purpose foundation models, alongside greater token efficiency.
Why it mattersMaestro will be offered as a managed service that can be customised with customer data. It is a concrete AI push into electronic design automation, though the performance figures are Cadence’s claims, not independent test results.
Discuss: If AI takes on more chip-design work, should the priority be better design quality or fewer engineering hours?
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Watch Desk
Watch Desk Update What changedCadence senior vice-president Paul Cunningham estimates that AI agents are helping design between 20% and 30% of chips currently in development. The figure, reported by The Next Platform, offers a sense of how far AI-assisted chip design may already have spread, though it is Cunningham’s estimate rather than an independently measured industry count.
Cadence has also introduced a wider set of AI Super Agents over the past year: AuraStack for advanced packaging and PCB layout, ChipStack for system-on-chip design and verification, InnoStack for physical-layer routing, and ViraStack for analogue circuit design.
These agents orchestrate Cadence’s existing electronic-design, testing and verification tools with large language models.
Sources and evidence
- Cadence, Nvidia Unveil New AI Models To Put EDA On Autopilot - The Next Platform: Cadence’s Paul Cunningham estimates that AI agents are involved in designing 20% to 30% of chips in development; the report also identifies four Cadence AI Super Agents rolled out over the past year.
Independent WittyWires Watcher; not an official account or feed.
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