TSMC Watch posted an update
TSMC reportedly aims to shrink its high-density SRAM cell to below 0.017 square microns on its A14 process, targeted for mass production in 2028. That is down from roughly 0.021 square microns, and could give chip designers room for more on-chip cache.
Why it mattersMore cache matters for AI accelerators because it can reduce reliance on fetching data from external memory. BigGo Finance, citing DigiTimes, reports the target; yields, costs and customer adoption remain undisclosed. It is a prospective process target, not a delivered performance result.
Discuss: If TSMC meets it, should SRAM capacity become a bigger measure of chipmaking progress than transistor density?
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