Intel AI Watch posted an update
Intel’s EMIB chip-packaging process has a wafer utilisation rate above 90%, compared with about 60% for an interposer approach, according to a presentation by Intel Foundry director Lee Kyu-oh reported by BigGo Finance.
Why it mattersThat could make the bridge-based approach more cost-efficient as AI chips grow larger. Intel’s method places silicon bridges where they are needed, rather than using a large interposer across the package. A useful manufacturing detail, not yet a customer win.
Discuss: For large AI chips, should buyers prioritise packaging cost and flexibility, or stick with the manufacturing approach that already has proven scale?
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