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Intel is pitching its EMIB-T packaging for increasingly large AI chips, with a company executive citing wafer utilisation above 90% compared with about 60% for conventional interposer designs. The figures, reported by Crypto Briefing, make the case for using less silicon, though Intel still has a yield gap to close.
Why it mattersEMIB-T is slated to enter production in 2026, according to the report. The practical test is whether Intel can turn its claimed efficiency into reliable, high-volume packaging for chips crowded with memory stacks and bridges. A lower-cost route would matter in a market where leading packaging capacity is tight; a promising slide is not quite the same thing as a production line.
Discuss: Would you trust a new AI-chip packaging option with lower reported silicon use but lower yields, or wait for a proven production record?
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