AI’s next bottleneck may be the package, not the processor

AI scaling is starting to look like a plumbing problem as much as a compute problem. TSMC says the next generation of densely packed AI systems could demand dramatically more power, forcing cooling and power delivery into the earliest stages of chip and package design.

TSMC Watch analysis

What happened

At SEMICON Taiwan 2026, TSMC Advanced Packaging R&D Director James Chen was reported as saying total AI-system power could rise around sixfold between 2024 and 2029. The same account puts package power at roughly 600W in 2024 and 4,100W by 2029, with power-delivery losses rising more than fivefold.

Those are projections, not observed outcomes. The supplied report is secondary, attributing the remarks through Anue and citing Taiwanese trade coverage, rather than reproducing a direct TSMC presentation.

Key findings

• Bigger packages, heavier loads
  CoWoS package size is projected to grow from 3.3 times reticle size to more than 14 times, while compute transistors per package rise around 48-fold.
• Bandwidth brings baggage
  HBM bandwidth per package is projected to increase more than 34-fold, driven by more I/Os and faster transfers.
• Cooling moves closer to the silicon
  TSMC is exploring microchannels in package lids, alongside jet impingement and two-phase boiling.
• Interfaces become suspects
  Thermal interface materials help bridge the chip, lid and cold plate, but add thermal resistance.
• Design starts earlier
  TSMC is reported to be co-optimising package structure, materials and hotspot placement, with thermal-resistance reductions of up to about 40% cited in the report.
• The supply chain gets wetter
  Higher-power systems could increase requirements for cold plates, manifolds, quick-disconnect couplings, coolant distribution units and heat exchangers.

Why it matters

Future AI capacity plans cannot treat cooling as a rack-level accessory bolted on after the interesting engineering is finished. Package power, facility power, liquid loops and maintenance requirements may need to be assessed together before a system is specified.

Microchannels are not a shipping product in this evidence. They are an R&D direction with difficult manufacturing and packaging trade-offs, where a small fabrication error could waste an expensive chip. The wager is that shortening the route between coolant and hotspot will eventually be worth the complexity.

Our read

This is a meaningful signal from the advanced-packaging frontier, not a promise that 4,100W packages are arriving on a warehouse pallet next Tuesday. Infrastructure planners should stress-test power and cooling assumptions now, while demanding measured thermal resistance, reliability, yield and maintenance data before treating the projections as procurement guidance.

What to watch

• TSMC publishing a direct technical roadmap or measured results for package-integrated microchannels.
• Accelerator and data-centre vendors disclosing package, rack and facility-power figures.
• Evidence of manufacturing yields, reliability and service requirements for the new cooling architectures.

Discussion spark: If package power approaches the levels described, which constraint should the industry solve first: cooling hardware, power delivery, packaging yield or system-level efficiency?

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