Credo and AMD demo terabyte-class memory for AI accelerators

Credo and AMD have built a working demonstration that gives an AMD programmable-logic AI accelerator access to terabyte-class memory, aimed at easing a bottleneck in AI inference. The intriguing part is that the demo is designed to expand memory capacity and bandwidth without changing application software or waiting for custom silicon.

Credo Technology Group Watch analysis

What happened

Credo says its OmniConnect Weaver memory technology is running on an AMD Versal AI Edge Series Gen 2 evaluation board. The system connects large pools of LPDDR memory to the programmable-logic processor over VSR links, using standard organic packaging without a silicon interposer.

The companies say the expanded memory is transparent above the controller, so application software runs unmodified. They are demonstrating the system at the 2026 OCP Global Summit. This is a working emulation platform, not evidence of a generally available product or a published performance result.

Why it matters

AI inference can be limited by how quickly a system can feed a model with data, not simply by how much computing power its accelerator offers. Credo’s proposal is to tackle that memory constraint while retaining the flexibility of programmable logic. If the approach scales beyond a demonstration, it could give system builders another way to support memory-hungry workloads without redesigning their applications around a new memory setup.

That makes this more than a chip-company handshake: it is a concrete attempt to widen the memory options available to AI hardware. The useful question now is whether the extra capacity and bandwidth translate into measurable gains on real workloads, at sensible power and cost.

Our read

The practical promise is compelling: more memory for inference, with existing software left alone. But “terabyte-class” describes capacity, not a result. Until the partners publish workload tests, throughput, power and cost comparisons, this remains a promising architecture demo rather than a proven shortcut around the memory wall. Still, it is exactly the sort of plumbing that can matter once models outgrow the neat limits of a single accelerator.

What to watch

• Whether Credo and AMD publish benchmark results on real inference workloads.
• What memory capacity, bandwidth and latency the system delivers in practice.
• Whether a product follows, and how its power and cost compare with alternatives.

Discussion spark: For AI inference, would you prioritise a larger shared memory pool, or a faster accelerator with a more conventional memory design?

not affiliated with or endorsed by Credo Technology Group