Architect Labs says AI designed an inference chip in under two weeks

An AI system has reportedly designed, verified and deployed a small inference-chip design from a written specification, with Architect Labs saying the flow took under two weeks. The practical significance is not that a chatbot has magically become a semiconductor foundry, but that hardware and software optimisation may be pulled into one much faster loop. VentureBeat's report describes the Redwood project and its early FPGA results.

Watch Desk analysis

What happened

According to the researchers, the Architect Labs Platform generated the digital hardware, tested and verified it, then produced firmware and kernels. Redwood has so far run on an FPGA, not fabricated silicon. Once specification changes were verified, modified designs could reportedly return to the FPGA in less than 48 hours.

The measured comparison is more modest than the headline promise. Redwood Nano delivered 12.1 tokens per second on Qwen3 0.6B at 250MHz, while an NVIDIA Jetson Orin Nano reached 28 tokens per second at 1,020MHz. The claimed advantage arrives only in a projection for a future Samsung 8nm-class implementation, which the researchers estimate could reach 49 tokens per second at roughly half the power. Architect Labs says it is working towards a tape-out at TSMC.

Key findings

• The design loop is the story
  The researchers say AI handled modelling, RTL generation, verification, firmware and kernels from a high-level specification.
• FPGA first, silicon later
  Redwood is demonstrated on programmable hardware; the projected fabricated-chip performance has not yet been tested.
• The current benchmark trails NVIDIA
  Redwood Nano's measured 12.1 tokens per second is below the Jetson Orin Nano's 28 in the reported comparison.
• The projected chip changes the maths
  The researchers estimate a future implementation could reach 49 tokens per second while drawing 1.335 watts versus 2.59 watts for the Jetson baseline.
• The system also tunes its own workload path
  The researchers report that a model running on Redwood found timing and kernel optimisations for later accelerator iterations.

Why it matters

Chip decisions normally harden long before anyone knows exactly which AI workloads will matter. A credible design system that can regenerate and reverify hardware quickly could let teams iterate around changing models rather than committing every assumption to a multi-year product cycle.

But the useful boundary is sharp. The supplied report describes an FPGA demonstration and projections for unbuilt silicon, not a shipping accelerator that has beaten NVIDIA. The next test is fabrication, post-silicon validation and performance on larger models.

Our read

This is one of the more interesting AI-for-hardware demonstrations because it attacks the whole design loop, not one tedious task inside it. The FPGA results show a serious prototype, while the performance-per-watt victory remains a forecast wearing a hard hat.

Readers evaluating the claim should separate what has run from what has been estimated: Redwood exists on programmable hardware; the 49-token-per-second result does not yet exist in silicon.

What to watch

• Whether Redwood reaches tape-out and post-silicon validation.
• Whether larger models reproduce the reported FPGA behaviour.
• Whether independent testing confirms the projected power and throughput figures.
• Whether AI-designed hardware can scale beyond this relatively small accelerator.

Discussion spark: If AI can shorten the hardware design loop but fabricated-silicon results remain uncertain, would you trust it first for specialised accelerators or for general-purpose chips?

Watch Desk is operated by WittyWires as an independent cross-cutting AI news tracker. It does not speak for the organisations or people it covers.