NVIDIA and Lorentz Solution will present a new chip-level electromagnetic verification workflow at TSMC’s Open Innovation Platform forum in Santa Clara on 23 September. The important bit is not another glossy AI slogan: as accelerator systems push data through optical and co-packaged interconnects at extreme speeds, the wiring itself becomes a performance and reliability problem.
NVIDIA Watch analysis
What happened
Lorentz says its PeakView platform can automate 3D full-wave electromagnetic extraction and sign-off directly from the layout database, then back-annotate models for advanced IC, 3DIC and silicon-photonics designs. The companies’ paper will focus on large-scale verification for the high-speed silicon used in AI data-centre systems. The supplied announcement says this is the third consecutive year Lorentz and NVIDIA have presented together at the TSMC OIP forum.
Key findings
- Interconnects become first-class engineering problems
At multi-terabit data rates, inductance, electromagnetic isolation and signal loss can undermine designs that look fine under simpler checks. - The workflow starts from the LVS database
Lorentz says its tool preserves connectivity across design hierarchies without requiring schematic or layout rework. - The target is AI-scale silicon
The announcement links the method to ultra-high-speed AI, silicon-photonics and custom 3DIC designs.
Why it matters
AI performance is not only about adding more accelerators. Those accelerators must exchange data quickly, cleanly and predictably, and the physical links between them can become the bottleneck. Better electromagnetic sign-off could help chip teams catch expensive interconnect problems before first silicon, particularly as advanced packaging and optical links carry more of the workload.
The practical boundary is important: this is a presentation and an announced design workflow, not an independent benchmark showing faster or more efficient AI systems.
Our read
This is a quietly important piece of the AI hardware stack. NVIDIA is helping push attention below the chip headline and into the wiring, packaging and verification work that determines whether ambitious systems behave in the real world. Read it as evidence of where engineering effort is moving, not as proof that every promised benefit has arrived.
What to watch
- Whether the companies publish concrete design sizes, runtimes or silicon results.
- Which AI, photonics or 3DIC designs are named as real-world case studies.
- Whether the workflow becomes part of broader NVIDIA or TSMC design ecosystems.
- How electromagnetic sign-off affects time to first silicon and packaging choices.
Discussion spark: As AI systems move towards optical and co-packaged links, should electromagnetic verification become a standard headline metric for accelerator designs?
Sources and evidence
- Lorentz Solution Jointly Presents with NVIDIA on Automated Large-Scale Chip-Level 3D EM Extraction and Sign-off of Ultra-High-Speed Silicon Photonics and IC/3DIC Designs at 2026 TSMC OIP – Yahoo Finance UK (14 September 2026, 15:30 UTC)
- Lorentz Solution source version (14 September 2026, 15:30 UTC)
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