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AMD’s Venice-X brings big cache and high clocks back to EPYC

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AMD is bringing its cache-heavy EPYC X chips back with Venice-X, due to begin shipping in the second half of 2027. The notable change: AMD says the design can combine a large L3 cache with higher clock speeds, rather than making HPC buyers choose between them.

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What happened

The Register reports that Venice-X will offer up to 96 cores and more than a gigabyte of L3 cache per socket. AMD’s design stacks SRAM beneath the processor chiplets, a change intended to avoid the heat constraint that previously limited clock speeds. AMD says Venice-X can reach 5.3GHz, compared with 3.7GHz for Genoa-X.

AMD is aiming the chips at latency-sensitive technical and scientific computing, including computational fluid dynamics and electronic design automation. The company expects shipments to start in the second half of 2027, so this is a product announcement, not a chip customers can order today.

Why it matters

Large caches can keep frequently used data closer to the processor, while higher clocks can help workloads that benefit from faster individual cores. Combining the two gives HPC operators another option for workloads where waiting on data movement or sacrificing frequency can be costly. The useful news is not simply that EPYC gets more cache, but that AMD says it has changed the packaging approach to avoid the old frequency trade-off.

Our read

Venice-X is a focused but meaningful server-CPU development. AMD’s figures are promising, but the real test will be performance on the scientific and engineering workloads it is targeting. For now, operators can put the announced specifications and 2027 timing on the roadmap, not in the procurement basket.

What to watch

  • Whether AMD publishes independent, workload-specific performance comparisons.
  • When the first Venice-X systems will be available to customers.
  • Whether the cache-and-clock combination proves useful beyond AMD’s stated HPC targets.

Discussion spark: For latency-sensitive HPC work, would you prioritise higher clock speeds, more cache, or evidence from workload-specific benchmarks before choosing a server CPU?

Sources and evidence

Independent WittyWires tracker for public updates about AMD. Not affiliated with or endorsed by AMD; this is not an official account.

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Update

What changed

The Register reports that Microsoft intends to deploy AMD’s Venice-X processors in Azure HXv2 instances starting next year. That adds a named cloud deployment and timeframe to the chip’s announced roadmap.

The report says the processors support DDR5-8000 memory and high-speed MRDIMMs on AMD’s SP7 platform.

It also specifies up to 1,152 MB of L3 cache per socket. These deployment and configuration details add useful information for cloud customers and operators planning future workloads.

Sources and evidence

Independent WittyWires Watcher; not an official account or feed.