TSMC plans to start using High-NA EUV lithography in high-volume manufacturing in 2030, according to reporting by Tom’s Hardware. The move matters because the technology can print finer features than today’s Low-NA EUV, but its smaller exposure field creates awkward engineering questions for enormous AI accelerators.
TSMC Watch analysis
What happened
TSMC has not said which process node will be first to use High-NA EUV. Tom’s Hardware identifies future A10 or A11-class technologies as plausible candidates, but that is analysis rather than a confirmed roadmap.
TSMC plans to begin with conventional 6×6-inch photomasks. It is also working towards a 6×12-inch format, with a pilot line targeted for 2031 and advanced-node production using the larger masks targeted for 2033.
– Sharper exposure High-NA EUV offers 8nm single-exposure resolution, compared with 13nm for current Low-NA EUV systems. – Smaller first step Conventional 6×6-inch masks halve the exposure field, complicating the manufacture of very large dies. – Bigger masks later Moving to 6×12-inch masks requires changes across EDA software, mask-making equipment and handling systems.
Why it matters
High-NA EUV is one of the less glamorous pieces of the AI hardware race, which is precisely why it deserves attention. Better lithography can help chipmakers pack more capability into each generation, but the reduced field size makes giant accelerators either a stitching problem or a chiplet problem.
The 6×12-inch transition is therefore not a mere change of ruler. It would require a broad tooling and software ecosystem to move in step, with implications for cost, throughput and energy efficiency.
Our read
TSMC’s 2030 commitment is a meaningful manufacturing signal, not proof that a particular A-series node is locked in. The interesting contest now is whether the industry can turn High-NA’s sharper resolution into practical, economical production without letting mask size and tool productivity become the bottleneck.
What to watch
- Which TSMC process node is formally named as the first High-NA EUV adopter.
- Whether TSMC confirms production volumes and scanner deployment timelines.
- Progress on 6×12-inch masks, including EDA and mask-writing support.
- Whether large AI chips favour stitching, chiplets or redesigned exposure layouts.
Discussion spark: Will High-NA EUV’s resolution gains outweigh the cost and complexity of smaller exposure fields for future AI accelerators?
Sources and evidence
- TSMC to start using High-NA EUV lithography in 2030 – A10 or A11 technology prime candidates for use – Tom's Hardware (8 September 2026, 15:00 UTC)
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